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? 2009 microchip technology inc. preliminary ds39948a pic18f87j93 family data sheet 64/80-pin, high-perfor mance microcontrollers with lcd driver, 12-bit a/d and nanowatt technology downloaded from: http:///
ds39948a-page ii preliminary ? 2009 microchip technology inc. information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, icepic, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, nanowatt xlp, omniscient code generation, picc, picc-18, pickit, picdem, picdem.net, pictail, pic 32 logo, real ice, rflab, select mode, total endurance, tsharc, wiperlock and zena are trademarks of micr ochip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2009, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specifications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconductor manufacturer c an guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are co mmitted to continuously improvi ng the code protection features of our products. attempts to break microchips c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory an d analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. downloaded from: http:///
? 2009 microchip technology inc. preliminary ds39948a-page 1 pic18f87j93 family lcd driver and keypad interface features: direct lcd panel drive capability: - can drive lcd panel while in sleep mode up to 48 segments and 192 pixels, software selectable programmable lcd timing module: - multiple lcd timing sources available - up to four commons: static, 1/2, 1/3 or 1/4 multiplex - static, 1/2 or 1/3 bias configuration on-chip lcd boost voltage regulator for contrast control charge time measurement unit (ctmu) for capacitive touch sensing adc for resistive touch sensing low-power features: power-managed modes: - run: cpu on, peripherals on - idle: cpu off, peripherals on - sleep: cpu off, peripherals off two-speed oscillator start-up flexible oscillator structure: two crystal modes, 4-25 mhz two external clock modes, up to 48 mhz 4x phase lock loop (pll) internal oscillator block with pll: - eight user-selectable frequencies from 31.25 khz to 8 mhz secondary oscillator using timer1 at 32 khz fail-safe clock monitor (fscm): - allows for safe shutdown if peripheral clock fails peripheral highlights: high-current sink/source 25 ma/25 ma (portb and portc) up to four external interrupts four 8-bit/16-bit timer/counter modules two capture/compare/pwm (ccp) modules master synchronous serial port (mssp) module with two modes of operation: - 3-wire/4-wire spi (supports all four spi modes) -i 2 c? master and slave mode one addressable usart module one enhanced addressable usart module: - lin/j2602 support - auto-wake-up on start bit and break character - auto-baud detect (abd) 12-bit, up to 12-channel a/d converter: - auto-acquisition - conversion available during sleep two analog comparators programmable reference voltage for comparators hardware real-time clock and calendar (rtcc) with clock, calendar and alarm functions charge time measurement unit (ctmu): - capacitance measurement - time measurement with 1 ns typical resolution note: this document is supplemented by the ?pic18f87j90 family data sheet? (ds39933). see section 1.0 ?device overview? . device flash program memory (bytes) sram data memory (bytes) i/o lcd (pixels) timers 8/16-bit ccp mssp eusart ausart 12-bit a/d (channels) comparators bor/lvd rtcc ctmu spi master i 2 c? PIC18F66J93 64k 3,923 51 132 1/3 2 yes yes 1/1 12 2 yes yes yes pic18f67j93 128k 3,923 51 132 1/3 2 yes yes 1/1 12 2 yes yes yes pic18f86j93 64k 3,923 67 192 1/3 2 yes yes 1/1 12 2 yes yes yes pic18f87j93 128k 3,923 67 192 1/3 2 yes yes 1/1 12 2 yes yes yes 64/80-pin, high-performanc e microcontrollers with lcd driver, 12-bit a/d and nanowatt technology downloaded from: http:///
pic18f87j93 family ds39948a-page 2 preliminary ? 2009 microchip technology inc. special microcontroller features: 10,000 erase/write cycle flash program memory, typical flash retention 20 years, minimum self-programmable under software control flash program memory has word write capability for data eeprom emulators priority levels for interrupts 8 x 8 single-cycle hardware multiplier extended watchdog timer (wdt): - programmable period from 4 ms to 131s in-circuit serial programming? (icsp?) via two pins in-circuit debug via two pins operating voltage range: 2.0v to 3.6v 5.5v tolerant input (digital pins only) selectable open-drain configuration for serial communication and ccp pins for driving outputs up to 5v on-chip 2.5v regulator downloaded from: http:///
? 2009 microchip technology inc. preliminary ds39948a-page 3 pic18f87j93 family pin diagrams ? pic18f6xj93 64-pin tqfp 50 49 lcdbias3 re3/com0 re4/com1 re5/com2 re6/com3 re7/ccp2 (1) /seg31 rd0/seg0/ctpls v dd v ss rd1/seg1 rd2/seg2 rd3/seg3 rd4/seg4 rd5/seg5 rd6/seg6 rd7/seg7 re1/lcdbias2 re0/lcdbias1 rg0/lcdbias0 rg1/tx2/ck2 rg2/rx2/dt2/v lcap 1 rg3/v lcap 2 mclr rg4/seg26/rtcc v ss v ddcore /v cap rf7/an5/ss /seg25 rf6/an11/seg24/c1ina rf5/an10/cv ref /seg23/c1inb rf4/an9/seg22/c2ina rf3/an8/seg21/c2inb rf2/an7/c1out/seg20 rb0/int0/seg30 rb1/int1/seg8 rb2/int2/seg9/cted1 rb3/int3/seg10/cted2 rb4/kbi0/seg11 rb5/kbi1/seg29 rb6/kbi2/pgc v ss osc2/clko/ra6 osc1/clki/ra7 v dd rb7/kbi3/pgd rc4/sdi/sda/seg16 rc3/sck/scl/seg17 rc2/ccp1/seg13 envreg rf1/an6/c2out/seg19 av dd av ss ra3/an3/v ref + ra2/an2/v ref - ra1/an1/seg18 ra0/an0 v ss v dd ra4/t0cki/seg14 ra5/an4/seg15 rc1/t1osi/ccp2 (1) /seg32 rc0/t1oso/t13cki rc7/rx1/dt1/seg28 rc6/tx1/ck1/seg27 rc5/sdo/seg12 54 53 52 51 58 57 56 55 60 59 64 63 62 61 note 1: the ccp2 pin placement depends on the ccp2mx configuration bit setting. PIC18F66J93 pic18f67j93 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 31 27 28 29 30 32 3837 36 35 34 33 4039 4847 46 45 44 43 42 41 downloaded from: http:///
pic18f87j93 family ds39948a-page 4 preliminary ? 2009 microchip technology inc. pin diagrams ? pic18f8xj93 80-pin tqfp 34 5 6 7 8 9 10 11 12 13 14 15 16 4847 46 45 44 43 42 41 40 39 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 lcdbias3 re3/com0 re4/com1 re5/com2 re6/com3 re7/ccp2 (1) /seg31 rd0/seg0/ctpls v dd v ss rd1/seg1 rd2/seg2 rd3/seg3 rd4/seg4 rd5/seg5 rd6/seg6 rd7/seg7 re1/lcdbias2 re0/lcdbias1 rg0/lcdbias0 rg1/tx2/ck2 rg2/rx2/dt2/v lcap 1 rg3/v lcap 2 mclr rg4/seg26/rtcc v ss v ddcore /v cap v ss osc2/clko/ra6 osc1/clki/ra7 v dd envreg rf1/an6/c2out/seg19 av dd av ss ra3/an3/v ref + ra2/an2/v ref - ra1/an1/seg18 ra0/an0 v ss v dd rj0 rj1/seg33 rh1/seg46 rh0/seg47 1 2 rh2/seg45 rh3/seg44 1718 rh7/seg43 rh6/seg42 rh5/seg41 rh4/seg40 rj5/seg38 rj4/seg39 37 rj7/seg36 rj6/seg37 5049 rj2/seg34 rj3/seg35 1920 33 34 35 36 38 5857 56 55 54 53 52 51 6059 68 67 66 65 72 71 70 69 74 73 78 77 76 75 79 80 rb0/int0/seg30 rb1/int1/seg8 rb2/int2/seg9/cted1 rb3/int3/seg10/cted2 rb4/kbi0/seg11 rb5/kbi1/seg29 rb6/kbi2/pgc rb7/kbi3/pgd rc2/ccp1/seg13 rc5/sdo/seg12 ra4/t0cki/seg14 ra5/an4/seg15 rc1/t1osi/ccp2 (1) i/seg32 rc0/t1oso/t13cki rc7/rx1/dt1/seg28 rc6/tx1/ck1/seg27 rf7/an5/ss /seg25 rf6/an11/seg24/c1ina rf5/an10/cv ref /seg23/c1inb rf4/an9/seg22/c2ina rf3/an8/seg21/c2inb rf2/an7/c1out/seg20 rc4/sdi/sda/seg16 rc3/sck/scl/seg17 note 1: the ccp2 pin placement depends on the ccp2mx configuration bit setting. pic18f86j93 pic18f87j93 downloaded from: http:///
? 2009 microchip technology inc. preliminary ds39948a-page 5 pic18f87j93 family table of contents 1.0 device overview ....................................................... ...................................................... ............................................................. 7 2.0 12-bit analog-to-digital converter (a/d) module ................................ ............................................. .......................................... 27 3.0 special features of the cpu........................................................ ......................................... ..................................................... 37 4.0 electrical characteristics .......................................................... ........................................ .......................................................... 39 5.0 packaging information........................................................ ............................................... ......................................................... 43 appendix a: revision history.......................................... ................................................... ...... ............................................................ 45 appendix b: device differences ........................................... ................................................... ... ......................................................... 45 appendix c: conversion considerations ............................................. ............................................. ................................................... 46 appendix d: migration from baseline to enhanced devices ............................... ......................................... ...................................... 46 index ................................................. ................................................... ...................... .......................................................................... 47 the microchip web site ....................................................................... .................................. .............................................................. 49 customer change notification service ....................................... ................................................... . ..................................................... 49 customer support............................................... ................................................... ............. ................................................................. 49 reader response ................................................. ................................................... ............ ................................................................ 50 product identification system ................................................. ..................................................................................................... ........ 51 downloaded from: http:///
pic18f87j93 family ds39948a-page 6 preliminary ? 2009 microchip technology inc. to our valued customers it is our intention to provide our valued customers with the be st documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regardi ng this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: microchips worldwide web site; http://www.microchip.com your local microchip sales office (see last page) when contacting a sales office, please specify which device, re vision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products. downloaded from: http:///
? 2009 microchip technology inc. preliminary ds39948a-page 7 pic18f87j93 family 1.0 device overview this document contains device-specific information for the following devices: the pic18f87j93 family of devices offers the advantages of all pic18 microcontrollers C high compu- tational performance, a rich feature set and economical price C with the addition of a versatile, on-chip lcd driver. these features make the pic18f87j93 family a logical choice for many high-performance applications where price is a primary consideration. 1.1 special features 12-bit a/d converter: the pic18f87j93 family implements a 12-bit a/d converter. a/d converters in both families incorporate programmable acquisi- tion time. this allows for a channel to be selected and a conversion to be initiated, without waiting for a sampling period and thus, reducing code overhead. data ram: the pic18f87j93 family devices have 3,923 bytes of ram. 1.2 details on individual family members devices in the pic18f87j93 family are available in 64-pin and 80-pin packages. block diagrams for the two groups are shown in figure 1-1 and figure 1-2. the devices are differentiated from each other in the following ways: flash program memory (64 kbytes for pic18fx6j93 devices and 128 kbytes for pic18fx7j93). lcd pixels: - 64-pin devices C 132 pixels (33 segs x 4 coms) - 80-pin devices C 192 pixels (48 segs x 4 coms) i/o ports (seven bidirectional ports on pic18f6xj93 devices and nine bidirectional ports on pic18f8xj93 devices). all other features for devices in this family are identical and are summarized in table 1-1 and table 1-2. the devices block diagrams are given in figure 1-1 and figure 1-2. the pinouts for all devices are listed in table 1-3 and table 1-4. PIC18F66J93 pic18f67j93 pic18f86j93 pic18f87j93 note: this data sheet documents only the devices features and specifications that are in addition to the features and specifications of the pic18f87j90 family devices. for information on the features and specifications shared by the pic18f87j93 family and pic18f87j90 family devices, see the ?pic18f87j90 family data sheet? (ds39933). downloaded from: http:///
pic18f87j93 family ds39948a-page 8 preliminary ? 2009 microchip technology inc. table 1-1: device features for the pic18f6xj93 (64-pin devices) table 1-2: device features for th e pic18f8xj93 (80-pin devices) features PIC18F66J93 pic18f67j93 operating frequency dc C 48 mhz program memory (bytes) 64k 128k program memory (instructions) 32,768 65,536 data memory (bytes) 3,923 3,923 interrupt sources 29 i/o ports ports a, b, c, d, e, f, g lcd driver (available pixels to drive) 132 (33 segs x 4 coms) timers 4 comparators 2 ctmu yes rtcc yes capture/compare/pwm modules 2 serial communications mssp, addressable usart, enhanced usart 12-bit analog-to-digital module 12 input channels resets (and delays) por, bor, reset instruction, stack full, stack underflow, mclr , wdt (pwrt, ost) instruction set 75 instructions, 83 with extended instruction set enabled packages 64-pin tqfp features pic18f86j93 pic18f87j93 operating frequency dc C 48 mhz program memory (bytes) 64k 128k program memory (instructions) 32,768 65,536 data memory (bytes) 3,923 3,923 interrupt sources 29 i/o ports ports a, b, c, d, e, f, g, h, j lcd driver (available pixels to drive) 192 (48 segs x 4 coms) timers 4 comparators 2 ctmu yes rtcc yes capture/compare/pwm modules 2 serial communications mssp, addressable usart, enhanced usart 12-bit analog-to-digital module 12 input channels resets (and delays) por, bor, reset instruction, stack full, stack underflow, mclr , wdt (pwrt, ost) instruction set 75 instructions, 83 with extended instruction set enabled packages 80-pin tqfp downloaded from: http:///
? 2009 microchip technology inc. preliminary ds39948a-page 9 pic18f87j93 family figure 1-1: pic18f6xj93 (64-pin) block diagram instruction decode and control porta data latch data memory (2.0, 3.9 address latch data address<12> 12 access bsr fsr0 fsr1 fsr2 inc/dec logic address 4 12 4 pch pcl pclath 8 31-level stack program counter prodl prodh 8 x 8 multiply 8 bitop 8 8 alu<8> address latch program memory (96 kbytes) data latch 20 8 8 table pointer<21> inc/dec logic 21 8 data bus<8> table latch 8 ir 12 3 pclatu pcu note 1: see table 1-3 for i/o port pin descriptions. 2: ra6 and ra7 are only available as digital i/os in select oscillator modes. 3: brown-out reset and low-voltage detect functions are provided when the on-board voltage regulator is enabled. ausart comparators mssp timer3 timer2 ctmu timer1 ccp2 adc 12-bit w instruction bus <16> stkptr bank 8 state machine control signals decode 8 8 eusart rom latch lcd portc portd porte portf portg ra0:ra7 (1,2) rc0:rc7 (1) rd0:rd7 (1) re0:re1, rf1:rf7 (1) rg0:rg4 (1) portb rb0:rb7 (1) osc1/clki osc2/clko v dd , timing generation v ss mclr power-up timer oscillator start-up timer power-on reset watchdog timer bor and lvd (3) precision reference band gap intrc oscillator regulator voltage v ddcore /v cap envreg kbytes) driver 8 mhz oscillator re3:re7 (1) timer0 ccp1 rtcc downloaded from: http:///
pic18f87j93 family ds39948a-page 10 preliminary ? 2009 microchip technology inc. figure 1-2: pic18f8xj93 (80-pin) block diagram instruction decode and control data latch data memory (2.0, 3.9 address latch data address<12> 12 access bsr fsr0 fsr1 fsr2 inc/dec logic address 4 12 4 pch pcl pclath 8 31-level stack program counter prodl prodh 8 x 8 multiply 8 bitop 8 8 alu<8> address latch program memory (96 kbytes) data latch 20 8 8 table pointer<21> inc/dec logic 21 8 data bus<8> table latch 8 ir 12 3 pclatu pcu w instruction bus <16> stkptr bank 8 state machine control signals decode 8 8 rom latch osc1/clki osc2/clko v dd , v ss mclr power-up timer oscillator start-up timer power-on reset watchdog timer precision reference band gap regulator voltage v ddcore /v cap envreg kbytes) porta portc portd porte portf portg ra0:ra7 (1,2) rc0:rc7 (1) rd0:rd7 (1) rf1:rf7 (1) rg0:rg4 (1) portb rb0:rb7 (1) porth rh0:rh7 (1) portj rj0:rj7 (1) note 1: see table 1-3 for i/o port pin descriptions. 2: ra6 and ra7 are only available as digital i/os in select oscillator modes. 3: brown-out reset and low-voltage detect functions are provided when the on-board voltage regulator is enabled. timing generation intrc oscillator 8 mhz oscillator re0:re1, re3:re7 (1) bor and lvd (3) ausart comparators mssp timer3 timer2 ctmu timer1 ccp2 adc 12-bit eusart lcd driver timer0 ccp1 rtcc downloaded from: http:///
? 2009 microchip technology inc. preliminary ds39948a-page 11 pic18f87j93 family table 1-3: pic18f6xj93 (64-pin de vice) pinout i/o descriptions pin name pin number pin type buffer type description tqfp mclr 7 i st master clear (input) or programming voltage (input). this pin is an active-low reset to the device. osc1/clki/ra7 osc1 clki ra7 39 ii i/o cmoscmos ttl oscillator crystal or external clock input. oscillator crystal input. external clock source input. always associated with pin function osc1. (see related osc1/clki, osc2/clko pins.) general purpose i/o pin. osc2/clko/ra6 osc2 clko ra6 40 oo i/o ttl oscillator crystal or clock output. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in ec modes, osc2 pin outputs clko, which has 1/4 the frequency of osc1 and denotes the instruction cycle rate. general purpose i/o pin. porta is a bidirectional i/o port. ra0/an0 ra0 an0 24 i/o i ttl analog digital i/o. analog input 0. ra1/an1/seg18 ra1 an1 seg18 23 i/o i o ttl analog analog digital i/o. analog input 1. seg18 output for lcd. ra2/an2/v ref - ra2 an2 v ref - 22 i/o ii ttl analog analog digital i/o. analog input 2. a/d reference voltage (low) input. ra3/an3/v ref + ra3 an3 v ref + 21 i/o ii ttl analog analog digital i/o. analog input 3. a/d reference voltage (high) input. ra4/t0cki/seg14 ra4 t0cki seg14 28 i/o i o stst analog digital i/o. timer0 external clock input. seg14 output for lcd. ra5/an4/seg15 ra5 an4 seg15 27 i/o i o ttl analog analog digital i/o. analog input 4. seg15 output for lcd. ra6 see the osc2/clko/ra6 pin. ra7 see the osc1/clki/ra7 pin. legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when the ccp2mx configuration bit is set. 2: alternate assignment for ccp2 when the ccp2mx configuration bit is cleared. downloaded from: http:///
pic18f87j93 family ds39948a-page 12 preliminary ? 2009 microchip technology inc. portb is a bidirectional i/o port. portb can be software programmed for internal weak pull-ups on all inputs. rb0/int0/seg30 rb0 int0 seg30 48 i/o i o ttl st analog digital i/o. external interrupt 0. seg30 output for lcd. rb1/int1/seg8 rb1 int1 seg8 47 i/o i o ttl st analog digital i/o. external interrupt 1. seg8 output for lcd. rb2/int2/seg9/cted1 rb2 int2 seg9 cted1 46 i/o i o i ttl st analog st digital i/o. external interrupt 2. seg9 output for lcd. ctmu edge 1 input. rb3/int3/seg10/cted2 rb3 int3 seg10 cted2 45 i/o i o i ttl st analog st digital i/o. external interrupt 3. seg10 output for lcd. ctmu edge 2 input. rb4/kbi0/seg11 rb4 kbi0 seg11 44 i/o i o ttlttl analog digital i/o. interrupt-on-change pin. seg11 output for lcd. rb5/kbi1/seg29 rb5 kbi1 seg29 43 i/o i o ttlttl analog digital i/o. interrupt-on-change pin. seg29 output for lcd. rb6/kbi2/pgc rb6 kbi2 pgc 42 i/o i i/o ttlttl st digital i/o. interrupt-on-change pin. in-circuit debugger and icsp? programming clock pin. rb7/kbi3/pgd rb7 kbi3 pgd 37 i/o i i/o ttlttl st digital i/o. interrupt-on-change pin. in-circuit debugger and icsp programming data pin. table 1-3: pic18f6xj93 (64-pin device) pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when the ccp2mx configuration bit is set. 2: alternate assignment for ccp2 when the ccp2mx configuration bit is cleared. downloaded from: http:///
? 2009 microchip technology inc. preliminary ds39948a-page 13 pic18f87j93 family portc is a bidirectional i/o port. rc0/t1oso/t13cki rc0 t1oso t13cki 30 i/o o i st st digital i/o. timer1 oscillator output. timer1/timer3 external clock input. rc1/t1osi/ccp2/seg32 rc1 t1osi ccp2 (1) seg32 29 i/o i i/o o st cmos st analog digital i/o. timer1 oscillator input. capture 2 input/compare 2 output/pwm2 output. seg32 output for lcd. rc2/ccp1/seg13 rc2 ccp1 seg13 33 i/oi/o o stst analog digital i/o. capture 1 input/compare 1 output/pwm1 output. seg13 output for lcd. rc3/sck/scl/seg17 rc3 sck scl seg17 34 i/oi/o i/o o stst st analog digital i/o. synchronous serial clock input/output for spi mode. synchronous serial clock input/output for i 2 c? mode. seg17 output for lcd. rc4/sdi/sda/seg16 rc4 sdi sda seg16 35 i/o i i/o o stst st analog digital i/o. spi data in. i 2 c data i/o. seg16 output for lcd. rc5/sdo/seg12 rc5 sdo seg12 36 i/o oo st analog digital i/o. spi data out. seg12 output for lcd. rc6/tx1/ck1/seg27 rc6 tx1 ck1 seg27 31 i/o o i/o o st st analog digital i/o. eusart asynchronous transmit. eusart synchronous clock (see related rx1/dt1). seg27 output for lcd. rc7/rx1/dt1/seg28 rc7 rx1 dt1 seg28 32 i/o i i/o o stst st analog digital i/o. eusart asynchronous receive. eusart synchronous data (see related tx1/ck1). seg28 output for lcd. table 1-3: pic18f6xj93 (64-pin device) pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when the ccp2mx configuration bit is set. 2: alternate assignment for ccp2 when the ccp2mx configuration bit is cleared. downloaded from: http:///
pic18f87j93 family ds39948a-page 14 preliminary ? 2009 microchip technology inc. portd is a bidirectional i/o port. rd0/seg0/ctpls rd0 seg0 ctpls 58 i/o oo st analog digital i/o. seg0 output for lcd. ctmu pulse generator output. rd1/seg1 rd1 seg1 55 i/o o st analog digital i/o. seg1 output for lcd. rd2/seg2 rd2 seg2 54 i/o o st analog digital i/o. seg2 output for lcd. rd3/seg3 rd3 seg3 53 i/o o st analog digital i/o. seg3 output for lcd. rd4/seg4 rd4 seg4 52 i/o o st analog digital i/o. seg4 output for lcd. rd5/seg5 rd5 seg5 51 i/o o st analog digital i/o. seg5 output for lcd. rd6/seg6 rd6 seg6 50 i/o o st analog digital i/o. seg6 output for lcd. rd7/seg7 rd7 seg7 49 i/o o st analog digital i/o. seg7 output for lcd. table 1-3: pic18f6xj93 (64-pin device) pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when the ccp2mx configuration bit is set. 2: alternate assignment for ccp2 when the ccp2mx configuration bit is cleared. downloaded from: http:///
? 2009 microchip technology inc. preliminary ds39948a-page 15 pic18f87j93 family porte is a bidirectional i/o port. re0/lcdbias1 re0 lcdbias1 2 i/o i st analog digital i/o. bias1 input for lcd. re1/lcdbias2 re1 lcdbias2 1 i/o i st analog digital i/o. bias2 input for lcd. lcdbias3 64 i analog bias3 input for lcd. re3/com0 re3 com0 63 i/o o st analog digital i/o. com0 output for lcd. re4/com1 re4 com1 62 i/o o st analog digital i/o. com1 output for lcd. re5/com2 re5 com2 61 i/o o st analog digital i/o. com2 output for lcd. re6/com3 re6 com3 60 i/o o st analog digital i/o. com3 output for lcd. re7/ccp2/seg31 re7 ccp2 (2) seg31 59 i/oi/o o stst analog digital i/o. capture 2 input/compare 2 output/pwm2 output. seg31 output for lcd. table 1-3: pic18f6xj93 (64-pin device) pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when the ccp2mx configuration bit is set. 2: alternate assignment for ccp2 when the ccp2mx configuration bit is cleared. downloaded from: http:///
pic18f87j93 family ds39948a-page 16 preliminary ? 2009 microchip technology inc. portf is a bidirectional i/o port. rf1/an6/c2out/seg19 rf1 an6 c2out seg19 17 i/o i oo st analog analog digital i/o. analog input 6. comparator 2 output. seg19 output for lcd. rf2/an7/c1out/seg20 rf2 an7 c1out seg20 16 i/o i oo st analog analog digital i/o. analog input 7. comparator 1 output. seg20 output for lcd. rf3/an8/seg21/c2inb rf3 an8 seg21 c2inb 15 i/o i o i st analog analog analog digital i/o. analog input 8. seg21 output for lcd. comparator 2 input b. rf4/an9/seg22/c2ina rf4 an9 seg22 c2ina 14 i/o i o i st analog analog analog digital i/o. analog input 9. seg22 output for lcd comparator 2 input a. rf5/an10/cv ref / seg23/c1inb rf5 an10 cv ref seg23 c1inb 13 i/o i oo i st analog analog analog analog digital i/o. analog input 10. comparator reference voltage output. seg23 output for lcd. comparator 1 input b. rf6/an11/seg24/c1ina rf6 an11 seg24 c1ina 12 i/o i o i st analog analog analog digital i/o. analog input 11. seg24 output for lcd comparator 1 input a. rf7/an5/ss /seg25 rf7 an5 ss seg25 11 i/o o i o st analog ttl analog digital i/o. analog input 5. spi slave select input. seg25 output for lcd. table 1-3: pic18f6xj93 (64-pin device) pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when the ccp2mx configuration bit is set. 2: alternate assignment for ccp2 when the ccp2mx configuration bit is cleared. downloaded from: http:///
? 2009 microchip technology inc. preliminary ds39948a-page 17 pic18f87j93 family portg is a bidirectional i/o port. rg0/lcdbias0 rg0 lcdbias0 3 i/o i st analog digital i/o. bias0 input for lcd. rg1/tx2/ck2 rg1 tx2 ck2 4 i/o o i/o st st digital i/o. ausart asynchronous transmit. ausart synchronous clock (see related rx2/dt2). rg2/rx2/dt2/v lcap 1 rg2 rx2 dt2 v lcap 1 5 i/o i i/o i stst st analog digital i/o. ausart asynchronous receive. ausart synchronous data (see related tx2/ck2). lcd charge pump capacitor input. rg3/v lcap 2 rg3 v lcap 2 6 i/o i st analog digital i/o. lcd charge pump capacitor input. rg4/seg26/rtcc rg4 seg26 rtcc 8 i/o oo st analog digital i/o. seg26 output for lcd. rtcc output v ss 9, 25, 41, 56 p ground reference for logic and i/o pins. v dd 26, 38, 57 p positive supply for logic and i/o pins. av ss 20 p ground reference for analog modules. av dd 19 p positive supply for analog modules. envreg 18 i st enable for on-chip voltage regulator. v ddcore /v cap v ddcore v cap 10 pp core logic power or external filter capacitor connection. positive supply for microcontroller core logic (regulator disabled). external filter capacitor connection (regulator enabled). table 1-3: pic18f6xj93 (64-pin device) pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when the ccp2mx configuration bit is set. 2: alternate assignment for ccp2 when the ccp2mx configuration bit is cleared. downloaded from: http:///
pic18f87j93 family ds39948a-page 18 preliminary ? 2009 microchip technology inc. table 1-4: pic18f8xj93 (80-pin de vice) pinout i/o descriptions pin name pin number pin type buffer type description tqfp mclr 9 i st master clear (input) or programming voltage (input). this pin is an active-low reset to the device. osc1/clki/ra7 osc1 clki ra7 49 ii i/o cmos cmos ttl oscillator crystal or external clock input. oscillator crystal input. external clock source input. always associated with pin function osc1. (see related osc1/clki, osc2/clko pins.) general purpose i/o pin. osc2/clko/ra6 osc2 clko ra6 50 oo i/o ttl oscillator crystal or clock output. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in ec modes, osc2 pin outputs clko, which has 1/4 the frequency of osc1 and denotes the instruction cycle rate. general purpose i/o pin. porta is a bidirectional i/o port. ra0/an0 ra0 an0 30 i/o i ttl analog digital i/o. analog input 0. ra1/an1/seg18 ra1 an1 seg18 29 i/o i o ttl analog analog digital i/o. analog input 1. seg18 output for lcd. ra2/an2/v ref - ra2 an2 v ref - 28 i/o ii ttl analog analog digital i/o. analog input 2. a/d reference voltage (low) input. ra3/an3/v ref + ra3 an3 v ref + 27 i/o ii ttl analog analog digital i/o. analog input 3. a/d reference voltage (high) input. ra4/t0cki/seg14 ra4 t0cki seg14 34 i/o i o stst analog digital i/o. timer0 external clock input. seg14 output for lcd. ra5/an4/seg15 ra5 an4 seg15 33 i/o i o ttl analog analog digital i/o. analog input 4. seg15 output for lcd. ra6 see the osc2/clko/ra6 pin. ra7 see the osc1/clki/ra7 pin. legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when the ccp2mx configuration bit is set. 2: alternate assignment for ccp2 when the ccp2mx configuration bit is cleared. downloaded from: http:///
? 2009 microchip technology inc. preliminary ds39948a-page 19 pic18f87j93 family portb is a bidirectional i/o port. portb can be software programmed for internal weak pull-ups on all inputs. rb0/int0/seg30 rb0 int0 seg30 58 i/o i o ttl st analog digital i/o. external interrupt 0. seg30 output for lcd. rb1/int1/seg8 rb1 int1 seg8 57 i/o i o ttl st analog digital i/o. external interrupt 1. seg8 output for lcd. rb2/int2/seg9/cted1 rb2 int2 seg9 cted1 56 i/o i o i ttl st analog st digital i/o. external interrupt 2. seg9 output for lcd. ctmu edge 1 input. rb3/int3/seg10/ cted2 rb3 int3 seg10 cted2 55 i/o i o i ttl st analog st digital i/o. external interrupt 3. seg10 output for lcd. ctmu edge 2 input. rb4/kbi0/seg11 rb4 kbi0 seg11 54 i/o i o ttl ttl analog digital i/o. interrupt-on-change pin. seg11 output for lcd. rb5/kbi1/seg29 rb5 kbi1 seg29 53 i/o i o ttl ttl analog digital i/o. interrupt-on-change pin. seg29 output for lcd. rb6/kbi2/pgc rb6 kbi2 pgc 52 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. in-circuit debugger and icsp? programming clock pin. rb7/kbi3/pgd rb7 kbi3 pgd 47 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. in-circuit debugger and icsp programming data pin. table 1-4: pic18f8xj93 (80-pin device) pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when the ccp2mx configuration bit is set. 2: alternate assignment for ccp2 when the ccp2mx configuration bit is cleared. downloaded from: http:///
pic18f87j93 family ds39948a-page 20 preliminary ? 2009 microchip technology inc. portc is a bidirectional i/o port. rc0/t1oso/t13cki rc0 t1oso t13cki 36 i/o o i st st digital i/o. timer1 oscillator output. timer1/timer3 external clock input. rc1/t1osi/ccp2/seg32 rc1 t1osi ccp2 (1) seg32 35 i/o i i/o o st cmos st analog digital i/o. timer1 oscillator input. capture 2 input/compare 2 output/pwm2 output. seg32 output for lcd. rc2/ccp1/seg13 rc2 ccp1 seg13 43 i/o i/o o stst analog digital i/o. capture 1 input/compare 1 output/pwm1 output. seg13 output for lcd. rc3/sck/scl/seg17 rc3 sck scl seg17 44 i/o i/o i/o o stst st analog digital i/o. synchronous serial clock input/output for spi mode. synchronous serial clock input/output for i 2 c? mode. seg17 output for lcd. rc4/sdi/sda/seg16 rc4 sdi sda seg16 45 i/o i i/o o stst st analog digital i/o. spi data in. i 2 c data i/o. seg16 output for lcd. rc5/sdo/seg12 rc5 sdo seg12 46 i/o oo st analog digital i/o. spi data out. seg12 output for lcd. rc6/tx1/ck1/seg27 rc6 tx1 ck1 seg27 37 i/o o i/o o st st analog digital i/o. eusart asynchronous transmit. eusart synchronous clock (see related rx1/dt1). seg27 output for lcd. rc7/rx1/dt1/seg28 rc7 rx1 dt1 seg28 38 i/o i i/o o stst st analog digital i/o. eusart asynchronous receive. eusart synchronous data (see related tx1/ck1). seg28 output for lcd. table 1-4: pic18f8xj93 (80-pin device) pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when the ccp2mx configuration bit is set. 2: alternate assignment for ccp2 when the ccp2mx configuration bit is cleared. downloaded from: http:///
? 2009 microchip technology inc. preliminary ds39948a-page 21 pic18f87j93 family portd is a bidirectional i/o port. rd0/seg0/ctpls rd0 seg0 ctpls 72 i/o oo st analog st digital i/o. seg0 output for lcd. ctmu pulse generator output. rd1/seg1 rd1 seg1 69 i/o o st analog digital i/o. seg1 output for lcd. rd2/seg2 rd2 seg2 68 i/o o st analog digital i/o. seg2 output for lcd. rd3/seg3 rd3 seg3 67 i/o o st analog digital i/o. seg3 output for lcd. rd4/seg4 rd4 seg4 66 i/o o st analog digital i/o. seg4 output for lcd. rd5/seg5 rd5 seg5 65 i/o o st analog digital i/o. seg5 output for lcd. rd6/seg6 rd6 seg6 64 i/o o st analog digital i/o. seg6 output for lcd. rd7/seg7 rd7 seg7 63 i/o o st analog digital i/o. seg7 output for lcd. table 1-4: pic18f8xj93 (80-pin device) pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when the ccp2mx configuration bit is set. 2: alternate assignment for ccp2 when the ccp2mx configuration bit is cleared. downloaded from: http:///
pic18f87j93 family ds39948a-page 22 preliminary ? 2009 microchip technology inc. porte is a bidirectional i/o port. re0/lcdbias1 re0 lcdbias1 4 i/o i st analog digital i/o. bias1 input for lcd. re1/lcdbias2 re1 lcdbias2 3 i/o i st analog digital i/o. bias2 input for lcd. lcdbias3 78 i analog bias3 input for lcd. re3/com0 re3 com0 77 i/o o st analog digital i/o. com0 output for lcd. re4/com1 re4 com1 76 i/o o st analog digital i/o. com1 output for lcd. re5/com2 re5 com2 75 i/o o st analog digital i/o. com2 output for lcd. re6/com3 re6 com3 74 i/o o st analog digital i/o. com3 output for lcd. re7/ccp2/seg31 re7 ccp2 (2) seg31 73 i/o i/o o stst analog digital i/o. capture 2 input/compare 2 output/pwm2 output. seg31 output for lcd. table 1-4: pic18f8xj93 (80-pin device) pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when the ccp2mx configuration bit is set. 2: alternate assignment for ccp2 when the ccp2mx configuration bit is cleared. downloaded from: http:///
? 2009 microchip technology inc. preliminary ds39948a-page 23 pic18f87j93 family portf is a bidirectional i/o port. rf1/an6/c2out/seg19 rf1 an6 c2out seg19 23 i/o i oo st analog analog digital i/o. analog input 6. comparator 2 output. seg19 output for lcd. rf2/an7/c1out/seg20 rf2 an7 c1out seg20 18 i/o i oo st analog analog digital i/o. analog input 7. comparator 1 output. seg20 output for lcd. rf3/an8/seg21/c2inb rf3 an8 seg21 c2inb 17 i/o i o i st analog analog analog digital i/o. analog input 8. seg21 output for lcd. comparator 2 input b. rf4/an9/seg22/c2ina rf4 an9 seg22 c2ina 16 i/o i o i st analog analog analog digital i/o. analog input 9. seg22 output for lcd. comparator 2 input a. rf5/an10/cv ref / seg23/c1inb rf5 an10 cv ref seg23 c1inb 15 i/o i oo i st analog analog analog analog digital i/o. analog input 10. comparator reference voltage output. seg23 output for lcd. comparator 1 input b. rf6/an11/seg24/c1ina rf6 an11 seg24 c1ina 14 i/o i o i st analog analog analog digital i/o. analog input 11. seg24 output for lcd. comparator 1 input a. rf7/an5/ss /seg25 rf7 an5 ss seg25 13 i/o o i o st analog ttl analog digital i/o. analog input 5. spi slave select input. seg25 output for lcd. table 1-4: pic18f8xj93 (80-pin device) pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when the ccp2mx configuration bit is set. 2: alternate assignment for ccp2 when the ccp2mx configuration bit is cleared. downloaded from: http:///
pic18f87j93 family ds39948a-page 24 preliminary ? 2009 microchip technology inc. portg is a bidirectional i/o port. rg0/lcdbias0 rg0 lcdbias0 5 i/o i st analog digital i/o. bias0 input for lcd. rg1/tx2/ck2 rg1 tx2 ck2 6 i/o o i/o st st digital i/o. ausart asynchronous transmit. ausart synchronous clock (see related rx2/dt2). rg2/rx2/dt2/v lcap 1 rg2 rx2 dt2 v lcap 1 7 i/o i i/o i stst st analog digital i/o. ausart asynchronous receive. ausart synchronous data (see related tx2/ck2). lcd charge pump capacitor input. rg3/v lcap 2 rg3 v lcap 2 8 i/o i st analog digital i/o. lcd charge pump capacitor input. rg4/seg26/rtcc rg4 seg26 rtcc 10 i/o oo st analog digital i/o. seg26 output for lcd. rtcc output. table 1-4: pic18f8xj93 (80-pin device) pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when the ccp2mx configuration bit is set. 2: alternate assignment for ccp2 when the ccp2mx configuration bit is cleared. downloaded from: http:///
? 2009 microchip technology inc. preliminary ds39948a-page 25 pic18f87j93 family porth is a bidirectional i/o port. rh0/seg47 rh0 seg47 79 i/o o st analog digital i/o. seg47 output for lcd. rh1/seg46 rh1 seg46 80 i/o o st analog digital i/o. seg46 output for lcd. rh2/seg45 rh2 seg45 1 i/o o st analog digital i/o. seg45 output for lcd. rh3/seg44 rh3 seg44 2 i/o o st analog digital i/o. seg44 output for lcd. rh4/seg40 rh4 seg40 22 i/o o st analog digital i/o. seg40 output for lcd. rh5/seg41 rh5 seg41 21 i/o o st analog digital i/o. seg41 output for lcd. rh6/seg42 rh6 seg42 20 i/o o st analog digital i/o. seg42 output for lcd. rh7/seg43 rh7 seg43 19 i/o o st analog digital i/o. seg43 output for lcd. table 1-4: pic18f8xj93 (80-pin device) pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when the ccp2mx configuration bit is set. 2: alternate assignment for ccp2 when the ccp2mx configuration bit is cleared. downloaded from: http:///
pic18f87j93 family ds39948a-page 26 preliminary ? 2009 microchip technology inc. portj is a bidirectional i/o port. rj0 62 i/o st digital i/o. rj1/seg33 rj1 seg33 61 i/o o st analog digital i/o. seg33 output for lcd. rj2/seg34 rj2 seg34 60 i/o o st analog digital i/o. seg34 output for lcd. rj3/seg35 rj3 seg35 59 i/o o st analog digital i/o. seg35 output for lcd. rj4/seg39 rj4 seg39 39 i/o o st analog digital i/o. seg39 output for lcd. rj5/seg38 rj5 seg38 40 i/o o st analog digital i/o seg38 output for lcd. rj6/seg37 rj6 seg37 41 i/o o st analog digital i/o. seg37 output for lcd. rj7/seg36 rj7 seg36 42 i/o o st analog digital i/o. seg36 output for lcd. v ss 11, 31, 51, 70 p ground reference for logic and i/o pins. v dd 32, 48, 71 p positive supply for logic and i/o pins. av ss 26 p ground reference for analog modules. av dd 25 p positive supply for analog modules. envreg 24 i st enable for on-chip voltage regulator. v ddcore /v cap v ddcore v cap 12 pp core logic power or external filter capacitor connection. positive supply for microcontroller core logic (regulator disabled). external filter capacitor connection (regulator enabled). table 1-4: pic18f8xj93 (80-pin device) pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when the ccp2mx configuration bit is set. 2: alternate assignment for ccp2 when the ccp2mx configuration bit is cleared. downloaded from: http:///
? 2009 microchip technology inc. preliminary ds39948a-page 27 pic18f87j93 family 2.0 12-bit analog-to-digital converter (a/d) module the analog-to-digital (a/d) converter module has 12 inputs for all pic18f87j93 family devices. this module allows conversion of an analog input signal to a corresponding 12-bit digital number. the module has these registers: a/d result high register (adresh) a/d result low register (adresl) a/d control register 0 (adcon0) a/d control register 1 (adcon1) a/d control register 2 (adcon2) the adcon0 register, shown in register 2-1, controls the operation of the a/d module. the adcon1 register, shown in register 2-2, configures the functions of the port pins. the adcon2 register, shown in register 2-3, configures the a/d clock source, programmed acquisition time and justification. register 2-1: adcon0: a/ d control register 0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adcal chs3 chs2 chs1 chs0 go/done adon bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 adcal: a/d calibration bit 1 = calibration is performed on next a/d conversion 0 = normal a/d converter operation (no calibration is performed) bit 6 unimplemented: read as 0 bit 5-2 chs<3:0>: analog channel select bits 0000 = channel 00 (an0) 0001 = channel 01 (an1) 0010 = channel 02 (an2) 0011 = channel 03 (an3) 0100 = channel 04 (an4) 0101 = channel 05 (an5) 0110 = channel 06 (an6) 0111 = channel 07 (an7) 1000 = channel 08 (an8) 1001 = channel 09 (an9) 1010 = channel 10 (an10) 1011 = channel 11 (an11) 11xx = unused bit 1 go/done : a/d conversion status bit when adon = 1 : 1 = a/d conversion in progress 0 = a/d idle bit 0 adon: a/d on bit 1 = a/d converter module is enabled 0 = a/d converter module is disabled downloaded from: http:///
pic18f87j93 family ds39948a-page 28 preliminary ? 2009 microchip technology inc. register 2-2: adcon1: a/ d control register 1 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 trigsel vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 trigsel: special trigger select bit 1 = selects the special trigger from the ctmu 0 = selects the special trigger from the ccp2 bit 6 unimplemented: read as 0 bit 5 vcfg1: voltage reference configuration bit (v ref - source) 1 =v ref - (an2) 0 =av ss bit 4 vcfg0: voltage reference configuration bit (v ref + source) 1 =v ref + (an3) 0 =av dd bit 3-0 pcfg<3:0>: a/d port configuration control bits: a = analog input d = digital i/o pcfg<3:0> an11 an10 an9 an8 an7 an6 an5 an4 an3 an2 an1 an0 0000 aaaaaaaaaaaa 0001 aaaaaaaaaaaa 0010 aaaaaaaaaaaa 0011 aaaaaaaaaaaa 0100 daaaaaaaaaaa 0101 ddaaaaaaaaaa 0110 dddaaaaaaaaa 0111 ddddaaaaaaaa 1000 dddddaaaaaaa 1001 ddddddaaaaaa 1010 dddddddaaaaa 1011 ddddddddaaaa 1100 dddddddddaaa 1101 ddddddddddaa 1110 ddddddddddda 1111 dddddddddddd downloaded from: http:///
? 2009 microchip technology inc. preliminary ds39948a-page 29 pic18f87j93 family register 2-3: adcon2: a/ d control register 2 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adfm acqt2 acqt1 acqt0 adcs2 adcs1 adcs0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 adfm: a/d result format select bit 1 = right justified 0 = left justified bit 6 unimplemented: read as 0 bit 5-3 acqt<2:0>: a/d acquisition time select bits 111 = 20 t ad 110 = 16 t ad 101 = 12 t ad 100 = 8 t ad 011 = 6 t ad 010 = 4 t ad 001 = 2 t ad 000 = 0 t ad (1) bit 2-0 adcs<2:0>: a/d conversion clock select bits 111 = f rc (clock derived from a/d rc oscillator) (1) 110 = f osc /64 101 = f osc /16 100 = f osc /4 011 = f rc (clock derived from a/d rc oscillator) (1) 010 = f osc /32 001 = f osc /8 000 = f osc /2 note 1: if the a/d f rc clock source is selected, a delay of one t cy (instruction cycle) is added before the a/d clock starts. this allows the sleep instruction to be executed before starting a conversion. downloaded from: http:///
pic18f87j93 family ds39948a-page 30 preliminary ? 2009 microchip technology inc. the analog reference voltage is software selectable to either the devices positive and negative supply voltage (av dd and av ss ) or the voltage level on the ra3/an3/ v ref + and ra2/an2/v ref - pins. the a/d converter has a unique feature of being able to operate while the device is in sleep mode. to operate in sleep, the a/d conversion clock must be derived from the a/ds internal rc oscillator. the output of the sample and hold is the input into the converter, which generates the result via successive approximation. each port pin associated with the a/d converter can be configured as an analog input or as a digital i/o. the adresh and adresl registers contain the result of the a/d conversion. when the a/d conversion is complete, the result is loaded into the adresh:adresl register pair, the go/done bit (adcon0<1>) is cleared and the a/d interrupt flag bit, adif, is set. a device reset forces all registers to their reset state. this forces the a/d module to be turned off and any conversion in progress is aborted. the value in the adresh:adresl register pair is not modified for a power-on reset. these registers will contain unknown data after a power-on reset. the block diagram of the a/d module is shown in figure 2-1. figure 2-1: a/d block diagram (1,2) (input voltage) v ain v ref + reference voltage av dd vcfg<1:0> chs<3:0> an7an6 an4 an3 an2 an1 an0 01110110 0100 0011 0010 0001 0000 12-bit a/d v ref - av ss converter an11 an10 an9 an8 10111010 1001 1000 note 1: channels an15 through an12 are not available on pic18f6xj93 devices. 2: i/o pins have diode protection to v dd and v ss . an5 0101 downloaded from: http:///
? 2009 microchip technology inc. preliminary ds39948a-page 31 pic18f87j93 family after the a/d module has been configured as desired, the selected channel must be acquired before the conversion is started. the analog input channels must have their corresponding tris bits selected as an input. to determine acquisition time, see section 2.1 ?a/d acquisition requirements? . after this acquisi- tion time has elapsed, the a/d conversion can be started. an acquisition time can be programmed to occur between setting the go/done bit and the actual start of the conversion. the following steps should be followed to do an a/d conversion: 1. configure the a/d module: configure analog pins, voltage reference and digital i/o (adcon1) select a/d input channel (adcon0) select a/d acquisition time (adcon2) select a/d conversion clock (adcon2) turn on a/d module (adcon0) 2. configure a/d interrupt (if desired): clear adif bit set adie bit set gie bit 3. wait the required acquisition time (if required). 4. start conversion: set go/done bit (adcon0<1>) 5. wait for a/d conversion to complete, by either: polling for the go/done bit to be cleared or waiting for the a/d interrupt 6. read a/d result registers (adresh:adresl); clear adif bit, if required. 7. for next conversion, go to step 1 or step 2, as required. the a/d conversion time per bit is defined as t ad . a minimum wait of 2 t ad is required before next acquisition starts. figure 2-2: analog input model v ain c pin r s anx 5 pf v dd v t = 0.6v v t = 0.6v i leakage r ic 1k sampling switch ss r ss c hold = 25 pf v ss sampling switch 123 4 (k ) v dd 100 na legend: c pin v t i leakage r ic ssc hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance (from dac) various junctions = sampling switch resistance r ss downloaded from: http:///
pic18f87j93 family ds39948a-page 32 preliminary ? 2009 microchip technology inc. 2.1 a/d acquisition requirements for the a/d converter to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 2-2. the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ). the source impedance affects the offset voltage at the ana- log input (due to pin leakage current). the maximum recommended impedance for analog sources is 2.5 k . after the analog input channel is selected (changed), the channel must be sampled for at least the minimum acquisition time before starting a conversion. to calculate the minimum acquisition time, equation 2-1 may be used. this equation assumes that 1/2 lsb error is used (1,024 steps for the a/d). the 1/2 lsb error is the maximum error allowed for the a/d to meet its specified resolution. equation 2-3 shows the calculation of the minimum required acquisition time, t acq . this calculation is based on the following application system assumptions: equation 2-1: acquisition time equation 2-2: a/d minimum charging time equation 2-3: calculating the minimum required acquisition time note: when the conversion is started, the holding capacitor is disconnected from the input pin. c hold =25 pf rs = 2.5 k conversion error 1/2 lsb v dd =3v rss = 2 k temperature = 85 c (system max.) t acq = amplifier settling time + holding capacitor charging time + temperature coeffici ent =t amp + t c + t coff v hold = (v ref C (v ref /2048)) (1 C e (-t c /c hold (r ic + r ss + r s )) ) or t c = -(c hold )(r ic + r ss + r s ) ln(1/2048) t acq =t amp + t c + t coff t amp =0.2 s t coff = (temp C 25 c)(0.02 s/ c) (85 c C 25 c)(0.02 s/ c) 1.2 s temperature coefficient is only required for temperatures > 25 c. below 25 c, t coff = 0 ms. t c = -(c hold )(r ic + r ss + r s ) ln(1/2048) s -(25 pf) (1 k + 2 k + 2.5 k ) ln(0.0004883) s 1.05 s t acq =0.2 s + 1 s + 1.2 s 2.4 s downloaded from: http:///
? 2009 microchip technology inc. preliminary ds39948a-page 33 pic18f87j93 family 2.2 selecting and configuring automatic acquisition time the adcon2 register allows the user to select an acquisition time that occurs each time the go/done bit is set. when the go/done bit is set, sampling is stopped and a conversion begins. the user is responsible for ensur- ing the required acquisition time has passed between selecting the desired input channel and setting the go/done bit. this occurs when the acqt<2:0> bits (adcon2<5:3>) remain in their reset state ( 000 ) and is compatible with devices that do not offer programmable acquisition times. if desired, the acqt bits can be set to select a programmable acquisition time for the a/d module. when the go/done bit is set, the a/d module continues to sample the input for the selected acquisition time, then automatically begins a conversion. since the acquisition time is programmed, there may be no need to wait for an acquisition time between selecting a channel and setting the go/done bit. in either case, when the conversion is completed, the go/done bit is cleared, the adif flag is set and the a/d begins sampling the currently selected channel again. if an acquisition time is programmed, there is nothing to indicate if the acquisition time has ended or if the conversion has begun. 2.3 selecting the a/d conversion clock the a/d conversion time per bit is defined as t ad . the a/d conversion requires 11 t ad per 12-bit conversion. the source of the a/d conversion clock is software selectable. there are seven possible options for t ad : 2 t osc 4 t osc 8 t osc 16 t osc 32 t osc 64 t osc internal rc oscillator for correct a/d conversions, the a/d conversion clock (t ad ) must be as short as possible but greater than the minimum t ad . table 2-1 shows the resultant t ad times derived from the device operating frequencies and the a/d clock source selected. table 2-1: t ad vs. device operating frequencies 2.4 configuring analog port pins the adcon1, trisa, trisf and trish registers control the operation of the a/d port pins. the port pins needed as analog inputs must have their correspond- ing tris bits set (input). if the tris bit is cleared (output), the digital output level (v oh or v ol ) will be converted. the a/d operation is independent of the state of the chs<3:0> bits and the tris bits. ad clock source (t ad )m a x i m u m device frequency operation adcs<2:0> 2 t osc 000 2.86 mhz 4 t osc 100 5.71 mhz 8 t osc 001 11.43 mhz 16 t osc 101 22.86 mhz 32 t osc 010 40.0 mhz 64 t osc 110 40.0 mhz rc (2) x11 1.00 mhz (1) note 1: the rc source has a typical t ad time of 4 s. 2: for device frequencies above 1 mhz, the device must be in sleep mode for the entire conversion or the a/d accuracy may be out of specification. note 1: when reading the port register, all pins configured as analog input channels will read as cleared (a low level). pins config- ured as digital inputs will convert an analog input. analog levels on a digitally configured input will be accurately converted. 2: analog levels on any pin defined as a digital input may cause the digital input buffer to consume current out of the devices specification limits. downloaded from: http:///
pic18f87j93 family ds39948a-page 34 preliminary ? 2009 microchip technology inc. 2.5 a/d conversions figure 2-3 shows the operation of the a/d converter after the go/done bit has been set and the acqt<2:0> bits are cleared. a conversion is started after the following instruction to allow entry into sleep mode before the conversion begins. figure 2-4 shows the operation of the a/d converter after the go/done bit has been set; the acqt<2:0> bits are set to 010 and a 4 t ad acquisition time is selected before the conversion starts. clearing the go/done bit during a conversion will abort the current conversion. the a/ d result register pair will not be updated with the partially completed a/d conversion sample. this means the adresh:adresl registers will continue to contain the value of the last completed conversion (or the last value written to the adresh:adresl registers). after the a/d conversion is completed or aborted, a 2t ad wait is required before the next acquisition can be started. after this wait, acquisition on the selected channel is automatically started. 2.6 use of the ccp2 trigger an a/d conversion can be started by the special event trigger of the ccp2 module. this requires that the ccp2m<3:0> bits (ccp2con<3:0>) be programmed as 1011 and that the a/d module is enabled (adon bit is set). when the trigger occurs, the go/done bit will be set, starting the a/d acquisition and conversion, and the timer1 (or timer3) counter will be reset to zero. timer1 (or timer3) is reset to automatically repeat the a/d acquisition period with minimal software overhead (moving adresh:adresl to the desired location). the appropriate analog input channel must be selected and the minimum acquisition period is either timed by the user, or an appropriate t acq time is selected before the special event trigger sets the go/done bit (starts a conversion). if the a/d module is not enabled (adon is cleared), the special event trigger will be ignored by the a/d module but will still reset the timer1 (or timer3) counter. figure 2-3: a/d conversion t ad cycles (acqt<2:0> = 000 , t acq = 0 ) figure 2-4: a/d conversion t ad cycles (acqt<2:0> = 010 , t acq = 4 t ad ) note: the go/done bit should not be set in the same instruction that turns on the a/d. t ad 1 t ad 2 t ad 3 t ad 4 t ad 5 t ad 6 t ad 7 t ad 8 t ad 11 set go/done bit holding capacitor is disconnected from analog input (typically 100 ns ) t ad 9 t ad 10 t cy - t ad next q4: adresh:adresl is loaded, go/done bit is cleared, adif bit is set, holding capacitor is connected to analog input. conversion starts b0 b9 b6 b5 b4 b3 b2 b1 b8 b7 1 2 3 4 5 6 7 8 11 set go/done bit (holding capacitor is disconnected) 9 10 next q4: adresh:adresl is loaded, go/done bit is cleared, adif bit is set, holding capacitor is reconnected to analog input. conversion starts 1 2 3 4 (holding capacitor continues acquiring input) t acqt cycles t ad cycles automatic acquisition time b0 b9 b6 b5 b4 b3 b2 b1 b8 b7 downloaded from: http:///
? 2009 microchip technology inc. preliminary ds39948a-page 35 pic18f87j93 family 2.7 a/d converter calibration the a/d converter in the pic18f87j93 family of devices includes a self-calibration feature which com- pensates for any offset generated within the module. the calibration process is automated and is initiated by setting the adcal bit (adcon0<7>). the next time the go/done bit is set, the module will perform a dummy conversion (which means it is reading none of the input channels) and store the resulting value internally to compensate for offset. thus, subsequent offsets will be compensated. the calibration process assumes that the device is in a relatively steady-state operating condition. if a/d calibration is used, it should be performed after each device reset or if there are other major changes in operating conditions. 2.8 operation in power-managed modes the selection of the automatic acquisition time and a/d conversion clock is determined in part by the clock source and frequency while in a power-managed mode. if the a/d is expected to operate while the device is in a power-managed mode, the acqt<2:0> and adcs<2:0> bits in adcon2 should be updated in accordance with the power-managed mode clock that will be used. after the power-managed mode is entered (either of the power-managed run modes), an a/d acquisition or conversion may be started. once an acquisition or conversion is started, the device should continue to be clocked by the same power-managed mode clock source until the conversion has been completed. if desired, the device may be placed into the corresponding power-managed idle mode during the conversion. if the power-managed mode clock frequency is less than 1 mhz, the a/d rc clock source should be selected. operation in sleep mode requires the a/d rc clock to be selected. if bits, acqt<2:0>, are set to 000 and a conversion is started, the conversion will be delayed one instruction cycle to allow execution of the sleep instruction and entry to sleep mode. the idlen and scsx bits in the osccon register must have already been cleared prior to starting the conversion. table 2-2: summary of a/d registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 notes intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 2 pir1 a d i f rc1if tx1if sspif tmr2if tmr1if 2 pie1 a d i e rc1ie tx1ie sspie tmr2ie tmr1ie 2 ipr1 a d i p rc1ip tx1ip sspip tmr2ip tmr1ip 2 pir3 lcdif rc2if tx2if ctmuif ccp2if ccp1if rtccif 2 pie3 lcdie rc2ie tx2ie ctmuie ccp2ie ccp1ie rtccie 2 ipr3 lcdip rc2ip tx2ip ctmuip ccp2ip ccp1ip rtccip 2 adresh a/d result register high byte 2 adresl a/d result register low byte 2 adcon0 adcal chs3 chs2 chs1 chs0 go/done adon 2 adcon1 trigsel vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 2 adcon2 adfm acqt2 acqt1 acqt0 adcs2 adcs1 adcs0 2 ccp2con dc2b1 dc2b0 ccp2m3 ccp2m2 ccp2m1 ccp2m0 2 porta ra7 (1) ra6 (1) ra5 ra4 ra3 ra2 ra1 ra0 2 trisa trisa7 (1) trisa6 (1) trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 2 portf rf7 rf6 rf5 rf4 rf3 rf2 rf1 2 trisf trisf5 trisf4 trisf5 t risf4 trisf3 trisf2 trisf1 2 legend: = unimplemented, read as 0 . shaded cells are not used for a/d conversion. note 1: ra<7:6> and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default clock source (fosc2 configuration bit = 0 ); otherwise, they are disabled and these bits read as 0 . 2: for these reset values, see section 4.0 ?reset? of the ?pic18f87j90 family data sheet? (ds39933). downloaded from: http:///
pic18f87j93 family ds39948a-page 36 preliminary ? 2009 microchip technology inc. notes: downloaded from: http:///
? 2009 microchip technology inc. preliminary ds39948a-page 37 pic18f87j93 family 3.0 special features of the cpu 3.1 device id registers the device id registers are read-only registers. they identify the device type and revision for device programmers and can be read by firmware using table reads. table 3-1: device id registers note 1: this section documents only the cpu features that are different from, or in addi- tion to, the features of the pic18f87j90 family devices. 2: for additional details on the configuration bits, refer to section 24.1 ?configuration bits? in the ?pic18f87j90 family data sheet? (ds39933). file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default/ unprogrammed value (1) 3ffffeh devid1 dev2 dev1 dev0 rev4 rev3 rev2 rev1 rev0 xxxx xxxx (2) 3fffffh devid2 dev10 dev9 dev8 dev7 dev6 dev5 dev4 dev3 0000 10x1 (2) legend: x = unknown, = unimplemented. shaded cells are unimplemented, read as 0 . note 1: values reflect the unprogrammed state as received from the factory and following power-on resets. in all other reset states, the configuration bytes maintain their previously programmed states. 2: see register 3-1 and register 3-2 for devid values. th ese registers are read-only and cannot be programmed by the user. downloaded from: http:///
pic18f87j93 family ds39948a-page 38 preliminary ? 2009 microchip technology inc. register 3-1: devid1: device id register 1 for pic18f87j93 family devices rrrrrrrr dev2 dev1 dev0 rev4 rev3 rev2 rev1 rev0 bit 7 bit 0 legend: r = read-only bit bit 7-5 dev<2:0>: device id bits 111 = pic18f87j93 110 = pic18f86j93 011 = pic18f67j93 010 = PIC18F66J93 bit 4-0 rev<4:0>: revision id bits these bits are used to indicate the device revision. register 3-2: devid2: device id register 2 for pic18f87j93 family devices rrrrrrrr dev10 (1) dev9 (1) dev8 (1) dev7 (1) dev6 (1) dev5 (1) dev4 (1) dev3 (1) bit 7 bit 0 legend: r = read-only bit bit 7-0 dev<10:3>: device id bits (1) these bits are used with the dev<2:0> bits in the device id register 1 to identify the part number. 0101 0000 = pic18f87j93 family devices note 1: the values for dev<10:3> may be shared with other device families. the specific device is always identified by using the entire dev<10:0> bit sequence. downloaded from: http:///
? 2009 microchip technology inc. preliminary ds39948a-page 39 pic18f87j93 family 4.0 electrical characteristics absolute maximum ratings (?) ambient temperature under bias................................................................................................. ............-40c to +100c storage temperature ............................................................................................................ .................. -65c to +150c voltage on any digital only i/o pin or mclr with respect to v ss (except v dd ) ........................................... -0.3v to 6.0v voltage on any combined digital and analog pin with respect to v ss (except v dd and mclr )...... -0.3v to (v dd + 0.3v) voltage on v ddcore with respect to v ss ................................................................................................... -0.3v to 2.75v voltage on v dd with respect to v ss ........................................................................................................... -0.3v to 3.6v total power dissipation (note 1) ............................................................................................................................... 1.0w maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin ..............................................................................................................................250 ma maximum output current sunk by porta<7:6> and any portb and portc i/o pins.........................................25 ma maximum output current sunk by any portd, porte and portj i/o pins ..........................................................8 ma maximum output current sunk by porta<5:0> and any portf, portg and porth i/o pins ............................2 m a maximum output current sourced by porta<7:6> and any portb and portc i/o pins ...................................25 ma maximum output current sourced by any portd, porte and portj i/o pins .....................................................8 ma maximum output current sourced by porta<5:0> and any portf, portg and porth i/o pins .......................2 ma maximum current sunk by all ports combined.......................................................................................................200 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd C i oh } + {(v dd C v oh ) x i oh } + (v ol x i ol ) note: other than some basic data, this section documents only the pic18f87j93 family devices specificatio ns that differ from those of the pic18f87j90 family devices. for detailed information on the electrical specifications shared by the pic18f87j93 family and pic18f87j90 family devices, see the ?pic18f87j90 family data sheet? (ds39933). ? notice: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the devi ce at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. downloaded from: http:///
pic18f87j93 family ds39948a-page 40 preliminary ? 2009 microchip technology inc. figure 4-1: voltage-fr equency graph, regulator enabled (industrial) (1) figure 4-2: voltage-fr equency graph, regulator disabled (industrial) (1) frequency voltage (v dd ) 4.0v 2.0v 48 mhz 3.5v 3.0v 2.5v 3.6v 2.35v 0 note 1: when the on-chip regulator is enabled, its bor circuit will automatically trigger a device reset before v dd reaches a level at which full-speed operation is not possible. 8 mhz pic18lf87j93 family frequency voltage (v ddcore ) 3.00v 2.00v 48 mhz 2.75v 2.50v 2.25v 2.7v 8 mhz 2.35v note 1: when the on-chip voltage regulator is disabled, v dd and v ddcore must be maintained so that v ddcore v dd 3.6v. pic18lf87j93 family downloaded from: http:///
? 2009 microchip technology inc. preliminary ds39948a-page 41 pic18f87j93 family table 4-1: a/d converter characteristics: pic18f87j93 family (industrial) param no. sym characteristic min typ max units conditions a01 n r resolution 12 bit v ref 3.0v a03 e il integral linearity error <1 2.0 lsb v ref 3.0v a04 e dl differential linearity error <1 1.5 lsb v ref 3.0v a06 e off offset error <1 5 lsb v ref 3.0v a07 e gn gain error <1 3 lsb v ref 3.0v a10 monotonicity guaranteed (1) v ss v ain v ref a20 v ref reference voltage range (v refh C v refl ) 3v dd C v ss v for 12-bit resolution a21 v refh reference voltage high v ss + 3.0v v dd + 0.3v v for 12-bit resolution a22 v refl reference voltage low v ss C 0.3v v dd C 3.0v v for 12-bit resolution a25 v ain analog input voltage v refl v refh v note 2 a30 z ain recommended impedance of analog voltage source 2 . 5k a50 i ref v ref input current (2) 5 150 a a during v ain acquisition. during a/d conversion cycle. note 1: the a/d conversion result never decreases with an in crease in the input voltage and has no missing codes. 2: v refh current is from the ra3/an3/v ref + pin or v dd , whichever is selected as the v refh source. v refl current is from the ra2/an2/v ref -/cv ref pin or v ss , whichever is selected as the v refl source. downloaded from: http:///
pic18f87j93 family ds39948a-page 42 preliminary ? 2009 microchip technology inc. figure 4-3: a/d conversion timing table 4-2: a/d conversion requirements param no. symbol characteristic min max units conditions 130 t ad a/d clock period 0.8 12.5 (1) st osc based, v ref 3.0v 131 t cnv conversion time (not including acquisition time) (2) 13 14 t ad 132 t acq acquisition time (3) 1.4 s 135 t swc switching time from convert sample (note 4) 137 t dis discharge time 0.2 s note 1: the time of the a/d clock period is dependent on the device frequency and the t ad clock divider. 2: adres registers may be read on the following t cy cycle. 3: the time for the holding capacitor to acquire the new input voltage wh en the voltage changes full scale after the conversion (v dd to v ss or v ss to v dd ). the source impedance (r s ) on the input channels is 50 . 4: on the following cycle of the device clock. 131 130 132 bsf adcon0, go q4 a/d clk (1) a/d data adres adif go sample old_data sampling stopped done new_data (note 2) 11 10 9 3 2 1 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 2: this is a minimal rc delay (typically 100 ns), which also disconnects the holding capa citor from the analog input. . . . . . . t cy 0 downloaded from: http:///
? 2009 microchip technology inc. preliminary ds39948a-page 43 pic18f87j93 family 5.0 packaging information for packaging information, see the ?pic18f87j93 family data sheet? (ds39933). downloaded from: http:///
pic18f87j93 family ds39948a-page 44 preliminary ? 2009 microchip technology inc. notes: downloaded from: http:///
? 2009 microchip technology inc. preliminary ds39948a-page 45 pic18f87j93 family appendix a: revision history revision a (june 2009) original data sheet for pic18f87j93 family devices. appendix b: device differences the differences between the devices listed in this data sheet are shown in table b-1. table b-1: pic18f87j93 family device differences features PIC18F66J93 pic18f67j93 pic18f86j93 pic18f87j93 program memory (bytes) 64k 128k 64k 128k program memory (instructions) 32768 65536 32768 65536 interrupt sources 28 28 29 29 i/o ports ports a, b, c, d, e, f, g ports a, b, c, d, e, f, g ports a, b, c, d, e, f, g, h , j ports a, b, c, d, e, f, g, h , j c a p t u r e / c o m p a r e / p w m m o d u l e s 2222 enhanced capture/compare/pwm modules 3333 packages 64-pin tqfp 64-pin tqfp 80-pin tqfp 80-pin tqfp downloaded from: http:///
pic18f87j93 family ds39948a-page 46 preliminary ? 2009 microchip technology inc. appendix c: conversion considerations this appendix discusses the considerations for converting from previous versions of a device to the ones listed in this data sheet. typically, these changes are due to the differences in the process technology used. an example of this type of conversion is from a pic16c74a to a pic16c74b. not applicable appendix d: migration from baseline to enhanced devices this section discusses how to migrate from a baseline device (such as the pic16c5x) to an enhanced mcu device (such as the pic18fxxx). the following are the list of modifications over the pic16c5x microcontroller family: not currently available downloaded from: http:///
ds39948a-page 47 preliminary ? 2009 microchip technology inc. pic18f87j93 family index a a/d a/d converter interrupt, configuring .......................... 31 acquisition requirements .......................................... . 32 adcal bit................................................................... 35 adcon0 register....................................................... 27 adcon1 register....................................................... 27 adcon2 register....................................................... 27 adresh register................................................. 27, 30 adresl register ....................................................... 27 analog port pins, configuring ..................................... 33 associated registers .................................................. 35 configuring the module ........................................... .... 31 conversion clock (t ad ) .............................................. 33 conversion status (go/done bit) ............................. 30 conversions ................................................................ 34 converter calibration .................................................. 35 converter characteristics ........................................... 41 operation in power-managed modes ......................... 35 overview ..................................................................... 27 selecting and configuring automatic acquisition time.................................................. 33 special event trigger (ccp)....................................... 34 use of the ccp2 trigger............................................ . 34 absolute maximum ratings ................................................ 39 adcal bit ........................................................................... 35 adcon0 register............................................................... 27 go/done bit.............................................................. 30 adcon1 register............................................................... 27 adcon2 register............................................................... 27 adresh register............................................................... 27 adresl register ......................................................... 27, 30 analog-to-digital converter. see a/d. b block diagrams a/d .............................................................................. 30 analog input model .............................................. ....... 31 PIC18F66J93/67j93 ..................................................... 9 pic18f86j93/87j93 ................................................... 10 c compare (ccp module) special event trigger.................................................. 34 conversion considerations ................................................. 46 customer change notification service ............................... 49 customer notification service............................................. 49 customer support ............................................... ................ 49 d device differences .............................................................. 45 device overview detailed features.......................................................... 7 features (64-pin devices) ............................................ 8 features (80-pin devices) ............................................ 8 special features ........................................................... 7 e electrical characteristics ................................... ................. 39 equations a/d acquisition time .................................................. 32 a/d minimum charging time...................................... 32 calculating the minimum required acquisition time ................................................. 32 errata .................................................................................... 6 f features summary device overview........................................................... 1 flexible oscillator structure....... ................................... 1 lcd driver and keypad interface................................. 1 low power .................................................................... 1 peripheral highlights.............................................. ....... 1 special microcontroller attributes ................................. 2 i internet address ................................................... .............. 49 interrupt sources a/d conversion complete .......................................... 31 m microchip internet web site................................................ 49 migration from baseline to enhanced devices.................. 46 p packaging information .................................................... .... 43 pin diagrams PIC18F66J93/67j93 ................................................ ..... 3 pic18f86j93/87j93 ................................................ ..... 4 pin functions av dd ........................................................................... 17 av dd ........................................................................... 26 av ss ........................................................................... 17 av ss ........................................................................... 26 envreg .............................................................. 1 7, 26 lcdbias3 ............................................................ 15, 22 mclr ................................................................... 11, 18 osc1/clki/ra7 ................................................... 11, 18 osc2/clko/ra6 ................................................. 11, 18 ra0/an0............................................................. .. 11, 18 ra1/an1/seg18 .................................................. 11 , 18 ra2/an2/v ref - .................................................... 11, 18 ra3/an3/v ref + ................................................... 11, 18 ra4/t0cki/seg14 ............................................... 11, 18 ra5/an4/seg15 .................................................. 11 , 18 rb0/int0/seg30 ................................................. 12, 19 rb1/int1/seg8 ................................................... 12, 19 rb2/int2/seg9/cted1....................................... 12, 19 rb3/int3/seg10/cted2..................................... 12, 19 rb4/kbi0/seg11 ................................................. 12, 19 rb5/kbi1/seg29 ................................................. 12, 19 rb6/kbi2/pgc ..................................................... 12, 19 rb7/kbi3/pgd ..................................................... 12, 19 rc0/t1oso/t13cki ............................................ 13, 20 downloaded from: http:///
pic18f87j93 family ds39948a-page 48 preliminary ? 2009 microchip technology inc. rc1/t1osi/ccp2/seg32 .................................... 13, 20 rc2/ccp1/seg13................................................ 13, 20 rc3/sck/scl/seg17 .......................................... 13, 20 rc4/sdi/sda/seg16 ........................................... 13, 20 rc5/sdo/seg12 ................................................. 13, 20 rc6/tx1/ck1/seg27........................................... 13, 20 rc7/rx1/dt1/seg28 .......................................... 13, 20 rd0/seg0/ctpls................................................ 14, 21 rd0/seg1 .................................................................. 14 rd1/seg1 .................................................................. 21 rd2/seg2 ............................................................ 14, 21 rd3/seg3 ............................................................ 14, 21 rd4/seg4 ............................................................ 14, 21 rd5/seg5 ............................................................ 14, 21 rd6/seg6 ............................................................ 14, 21 rd7/seg7 ............................................................ 14, 21 re0/lcdbias1..................................................... 15, 22 re1/lcdbias2..................................................... 15, 22 re3/com0............................................................ 15, 22 re4/com1............................................................ 15, 22 re5/com2............................................................ 15, 22 re6/com3............................................................ 15, 22 re7/ccp2/seg31 ................................................ 15, 22 rf1/an6/c2out/seg19 ..................................... 16, 23 rf2/an7/c1out/seg20 ..................................... 16, 23 rf3/an8/seg21/c2inb ....................................... 16, 23 rf4/an9/seg22/c2ina ....................................... 16, 23 rf5/an10/cv ref /seg23/c1inb ......................... 16, 23 rf6/an11/seg24/c1ina ..................................... 16, 23 rf7/an5/ss /seg25 ............................................. 16, 23 rg0/lcdbias0 .................................................... 17, 24 rg1/tx2/ck2 ....................................................... 17, 24 rg2/rx2/dt2/v lcap 1 .......................................... 17, 24 rg3/v lcap 2.......................................................... 17, 24 rg4/seg26/rtcc ............................................... 17, 24 rh0/seg47 ................................................................ 25 rh1/seg46 ................................................................ 25 rh2/seg45 ................................................................ 25 rh3/seg44 ................................................................ 25 rh4/seg40 ................................................................ 25 rh5/seg41 ................................................................ 25 rh6/seg42 ................................................................ 25 rh7/seg43 ................................................................ 25 rj0.............................................................................. 26 rj1/seg33 ................................................................. 26 rj2/seg34 ................................................................. 26 rj3/seg35 ................................................................. 26 rj4/seg39 ................................................................. 26 rj5/seg38 ................................................................. 26 rj6/seg37 ................................................................. 26 rj7/seg36 ................................................................. 26 v dd ............................................................................. 17 v dd ............................................................................. 26 v ddcore /v cap ...................................................... 17, 26 v ss .............................................................................. 17 v ss .............................................................................. 26 pinout i/o descriptions pic18f6xj93 ............................................................. 1 1 pic18f8xj93 ............................................................. 1 8 product identification system ........................................ ..... 51 r reader response................................................. .............. 50 registers adcon0 (a/d control 0)........................................... . 27 adcon1 (a/d control 1)........................................... . 28 adcon2 (a/d control 2)........................................... . 29 devid1 (device id 1)................................................. 38 devid2 (device id 2)................................................. 38 revision history...................................................... ............ 45 s special features of the cpu ................................. ............. 37 t timing diagrams a/d conversion........................................................... 42 timing diagrams and specifications a/d conversion requirements ................................... 42 v voltage-frequency graphs regulator disabled, industrial..................................... 40 regulator enabled, industrial ..................................... 40 w worldwide sales and service offices................................. 52 www address ............................................................... .... 49 www, on-line support ......... .............................................. 6 downloaded from: http:///
? 2009 microchip technology inc. preliminary ds39948a-page 49 pic18f87j93 family the microchip web site microchip provides online support via our www site at www.microchip.com. this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: product support C data sheets and errata, application notes and sample programs, design resources, users guides and hardware support documents, latest software releases and archived software general technical support C frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing business of microchip C product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchips customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: distributor or representative local sales office field application engineer (fae) technical support development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://support.microchip.com downloaded from: http:///
pic18f87j93 family ds39948a-page 50 preliminary ? 2009 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microc hip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our document ation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this docume nt. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds39948a pic18f87j93 family 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? downloaded from: http:///
? 2009 microchip technology inc. preliminary ds39948a-page 51 pic18f87j93 family product identification system to order or obtain purchasing informatio n such as pricing or delivery, refer to the factory or the listed sales office . part no. x /xx xxx pattern package temperature range device device (1,2) PIC18F66J93, PIC18F66J93t pic18f67j93, pic18f67j93t pic18f86j93, pic18f86j93t pic18f87j93, pic18f87j93t temperature range i = -40 c to +85 c (industrial) package pt = tqfp (thin quad flatpack) pattern qtp, sqtp, code or special requirements (blank otherwise) examples: a) pic18f87j93-i/pt 301 = industrial temperature, tqfp package, qtp pattern #301. b) pic18f87j93t-i/pt = tape and reel, industrial temperature, tqfp package. note 1: f = standard voltage range 2: t = in tape and reel downloaded from: http:///
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